Acquired Skills

1. You’ll be Familiar with Verilog HDL and System Verilog for designing and verifying SoCs.
2. Familiar with Verification stages such as writing test benches and test plans.
3. Familiar with Python scripting in field of chip design.
4. Familiar with Linux environment and shell scripts.
5. Creating coverage reports for measuring the completeness of the verification.
6. Utilizing commercial tools, e.g. Synopsys tools in designing and verifying SoCs.

Target Group

Computer, Electrical, Telecommunication, Mechatronics Engineering student or any other related fields.

Requirements

No prior experience is required.

Course Duration/Hours

90 Hour